1. Field of the Invention
The present invention relates to a semiconductor memory device which uses a resistive memory element as a memory cell and writes information by using an electric current flowing through the resistive memory element and, more particularly, to the structure and arrangement of a memory cell in which paired bit lines connected to the two terminals of the memory cell are formed by the same interconnection layer.
2. Description of the Related Art
Recently, semiconductor memories such as a PRAM (Phase change Random Access Memory) and MRAM (Magnetoresistive Random Access Memory) using resistive elements as memory elements are attracting attention and developed. The former is a semiconductor memory that stores information by changing the resistance value of a resistive memory element by changing the phase of the crystal structure of the element by supplying a write current to it. The latter is a semiconductor memory that uses, as a memory element, a magnetoresistive element having a structure called an MTJ (Magnetic Tunnel Junction) in which two ferromagnetic materials sandwich an insulating film, the magnetization direction in one ferromagnetic layer (a fixed layer) is fixed, and the magnetization direction in the other ferromagnetic layer (a recording layer) is reversible. This semiconductor memory stores information by using a so-called magnetoresistive effect by which the resistance value changes in accordance with relative magnetization directions in the recording layer and fixed layer. In particular, the MRAM has the characteristics that it is nonvolatile, can operate at a high speed, can be highly integrated, and has high reliability. Therefore, the MRAM is expected and developed as a memory device capable of replacing the SRAM, PSRAM (Pseudo SRAM), DRAM, and the like.
Conventionally, a so-called current-induced magnetic field write method is the general write method of the MRAM (e.g., non-patent reference 1). This write method reverses the magnetization direction in the recording layer by a magnetic field induced by an electric current flowing through a write line. On the other hand, this method has the problems that, e.g., the write current is large because the method is an indirect write method, and the write current increases when the MTJ element is downsized because a reversing magnetic field required to cause magnetization reversal in the recording layer increases.
As a method that solves these problems, a so-called spin injection MRAM using magnetization reversal caused by polarized spin current injection is attracting attention and developed (e.g., patent reference 1). In this method, the density of an electric current flowing through a magnetoresistive element defines a current amount (reversing threshold current) necessary for spin injection magnetization reversal. Accordingly, the reversing threshold current reduces as the area of the magnetoresistive element reduces. That is, the method is expected as a technique capable of implementing a large-capacity semiconductor memory, since the reversing threshold current is also scaled.
The write operation of the spin injection MRAM is performed by supplying a write current equal to or larger than the reversing threshold current to the magnetoresistive element, and the direction of the write current flowing through the magnetoresistive element determines the data polarity. In a general 1 Tr+1 MTJ memory cell, for example, one terminal of the MTJ element is connected to a first bit line, the other terminal of the MTJ element is connected to one source/drain electrode of a transistor, and the other source/drain electrode of the transistor is connected to a second bit line. In the conventional device, the first and second bit lines connected to the two terminals of the cell are formed by different interconnection layers. This makes the number of interconnection layers forming the bit lines larger than those of other semiconductor memories such as the DRAM, thereby posing problems such as a high process cost and a long chip formation period.    [Non-patent Reference 1] 2004 Symposium on VLSI Circuits Digest of Technical Papers, pp. 454-457, 2003 IEDM Proceedings, pp. 995-997    [Patent Reference 1] U.S. Pat. No. 5,695,864